82801BA Datasheet, PDF (213/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any
time. The ICH2 implements write posting on I/O writes across the AC-link (i.e., writes across the
link are indicated as complete before they are actually sent across the link). To prevent a second
I/O write from occurring before the first one is complete, software must monitor the CAS bit in the
Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS
bit is cleared, then another codec access (read or write) can go through. The exception is reads to
offset 54h/D4h (slot 12) which are returned immediately with the most recently received slot 12
data. Writes to offset 54h and D4h (primary and secondary codecs), get transmitted across the
AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect
the data being written.
The controller will not issue back-to-back reads. It must get a response to the first read before
issuing a second. In addition, codec reads and writes are only executed once across the link, and are
not repeated.
5.18.2 AC-Link Low Power Mode
The AC-link signals can be placed in a low power mode. When the AC‘97 Powerdown Register
(26h), is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to and
held at a logic low voltage level.
Figure 5-23. AC-link Powerdown Timing
SYNC
BIT_CLK
SDOUT
slot 12
prev. frame
TAG
Write to Data
0x20
PR4
SDIN
slot 12
prev. frame
TAG
Note:
BIT_CLK not to scale
BIT_CLK and SDIN transition low immediately following a write to the Powerdown Register
(26h) with PR4. When the AC‘97 controller driver is at the point where it is ready to program the
AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio
output frame.
The AC‘97 controller also drives AC_SYNC, and SDOUT low after programming AC‘97 to this
low power, halted mode. Once the codec has been instructed to halt BIT_CLK, a special wake up
protocol must be used to bring the AC-link to the active mode since normal output and input
frames can not be communicated in the absence of BIT_CLK. Once in a low power mode, the
ICH2 provides three methods for waking up the AC-link; external wake event, cold reset and warm
reset.
Note: Before entering any low power mode where the link interface to the codec is expected to be
powered down while the rest of the system is awake, the software must set the "Shut Off" bit in the
control register.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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