82801BA Datasheet, PDF (380/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
11.2.7 PORTSC[0,1]—Port Status and Control Register
I/O Offset:
Default Value:
Port 0/2: Base + (10–11h)
Port 1/3: Base + (12–13h)
0080h
Attribute:
Size:
R/W (Word writes only)
16 bits
Note: For Function 2, this applies to ICH2 USB ports 0 and 1. For Function 4, this applies to ICH2 USB
ports 2 and 3.
After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: no
device connected, Port disabled, and the bus line status is 00 (single-ended zero).
Bit
Description
15:13
12
11
10
9
8
7
6
5:4
Reserved—RO.
Suspend—R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the
USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows:
Bits [12,2]
X0
01
11
Hub State
Disable
Enable
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for single-
ended 0 resets (global reset and port reset). The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the
port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
1 = Port in suspend state.
0 = Port not in suspend state.
Note: Normally, if a transaction is in progress when this bit is set, the port will be suspended when
the current transaction completes. However, in the case of a specific error condition (out transaction
with babble), the ICH2 may issue a start-of-frame, and then suspend the port.
Overcurrent Indicator—R/WC. Set by hardware
1 = Overcurrent pin has gone from inactive to active on this port.
0 = Software clears this bit by writing a 1 to the bit position.
Overcurrent Active—RO. This bit is set and cleared by hardware.
1 = Indicates that the overcurrent pin is active (low).
0 = Indicates that the overcurrent pin is inactive (high).
Port Reset—RO.
1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.
0 = Port is not in Reset.
Low Speed Device Attached (LS)—RO. Writes have no effect.
1 = Low speed device is attached to this port.
0 = Full speed device is attached.
Reserved—RO. Always read as 1.
Resume Detect (RSM_DET)—R/W. Software sets this bit to a 1 to drive resume signaling. The
Host Controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while
the port is in the Suspend state. The ICH2 then reflects the K-state back onto the bus as long as the
bit remains a 1 and the port is still in the suspend state (bit 12,2 are 11). Writing a 0 (from 1) causes
the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed.
1 = Resume detected/driven on port.
0 = No resume (K-state) detected/driven on port.
Line Status—RO. These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’ logical levels. These
bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at
EOF2 time (See Chapter 11 of the USB Specification).
11-14
82801BA ICH2 and 82801BAM ICH2-M Datasheet