82801BA Datasheet, PDF (410/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Audio Controller Registers (D31:F5)
Bit
Description
PCM Out Interrupt (POINT)—RO. This bit indicates that one of the PCM out channel interrupts
occurred.
6
1 = Interrupt occurred.
0 = When the specific interrupt is cleared, this bit will be cleared.
PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts
occurred.
5
1 = Interrupt occurred.
0 = 0 = When the specific interrupt is cleared, this bit will be cleared.
4:3 Reserved
Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel
interrupts occurred.
2
1 = Interrupt occurred.
0 = When the specific interrupt is cleared, this bit will be cleared.
Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts
occurred.
1
1 = Interrupt occurred.
0 = When the specific interrupt is cleared, this bit will be cleared.
GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set
whenever bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined
0
as inputs changes.
1 = Input changed.
0 = Cleared by writing a 1 to this bit position.
13.2.10
CAS—Codec Access Semaphore Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 34h
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
7:1 Reserved.
Codec Access Semaphore (CAS)—R/W (special). This bit is read by software to check whether a
codec access is currently in progress.
0
0 = No access in progress.
1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform
an I/O access. Once the access is completed, hardware automatically clears this bit.
13-16
82801BA ICH2 and 82801BAM ICH2-M Datasheet