82801BA Datasheet, PDF (334/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.12
GPE1_EN—General Purpose Event 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Eh
(ACPI GPE1_BLK + 2)
0000h
No
Resume
Attribute:
Size:
Usage:
R/W
16-bit
ACPI
Note: This register is symmetrical to the General Purpose Event 1 Status Register. GPIOs that are not
implemented will not have the corresponding bits implemented in this register. All of the bits in
this register will be cleared by RSMRST#.
Note: Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.
9.8.3.13
Bit
Description
GPI[15:6] Enable (GPI[15:6]_EN)—R/W.
15:6 ^{1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.}
0 = Disable.
5 Reserved
GPI[4:3] Enable (GPI[4:3]_EN)—R/W.
4:3 ^{1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.}
0 = Disable.
2 Reserved
GPI[1:0] Enable (GPI[1:0]_EN)—R/W.
1:0 ^{1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.}
0 = Disable.
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 30h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
32 bit
ACPI or Legacy
Bit
Description
31:15
14
13
12
11
10:8
Reserved
Periodic SMI# Enable (PERIODIC_EN)—R/W.
0 = Disable.
1 = Enables the ICH2 to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS
register.
TCO Enable (TCO_EN)—R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are
caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0,
NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
Reserved
Microcontroller SMI# Enable (MCSMI_EN)—R/W.
0 = Disable.
1 = Enables ICH2 to trap accesses to the microcontroller range (62h or 66h) and generate an
SMI#. Note that ’trapped’ cycles will be claimed by the ICH2 on PCI, but not forwarded to LPC.
Reserved
9-72
82801BA ICH2 and 82801BAM ICH2-M Datasheet