82801BA Datasheet, PDF (252/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.4
8.1.5
PD_STS—Primary Device Status Register
(HUB-PCI—D30:F0)
Offset Address: 06–07h
Default Value: 0080h
Attribute:
Size:
R/WC
16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
Bit
Description
Detected Parity Error (DPE)—R/WC.
1 = Indicates that the ICH2 detected a parity error on the hub interface. This bit gets set even if the
15
Parity Error Response bit (offset 04, bit 6) is not set.
0 = Software clears this bit by writing a 1 to the bit location.
Received System Error (SSE)—R/WC.
1 = An address, or command parity error, or special cycles data parity error has been detected on
the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set
14
because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH2
will generate an NMI (or SMI# if NMI routed to SMI#)
0 = Software clears this bit by writing a 1 to the bit location.
Received Master Abort (RMA)—R/WC.
13 ^{1 = ICH2 received a master abort from the hub interface device.}
0 = Software clears this bit by writing a 1 to the bit location.
Received Target Abort (RTA)—R/WC.
1 = ICH2 received a target abort from the hub interface device. The TCO logic can cause an SMI#,
12
NMI, or interrupt based on this bit getting set.
0 = Software clears this bit by writing a 1 to the bit location.
Signaled Target Abort (STA)—R/WC.
11 ^{1 = ICH2 signals a target abort condition on the hub interface.}
0 = Software clears this bit by writing a 1 to the bit location.
DEVSEL# Timing Status—RO.
10:9
00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter.
Data Parity Error Detected (DPD)—R/WC. Since this register applies to the hub interface, the
ICH2 must interpret this bit differently than it is in the PCI specification.
8
1 = ICH2 detects a parity error on the hub interface and the Parity Error Response bit in the
Command Register (offset 04h, bit 6) is set.
0 = Software clears this bit by writing a 1 to the bit location.
7 Fast Back to Back—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable—RO. Hardwired to 0.
4:0 Reserved.
REVID—Revision ID Register (HUB-PCI—D30:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
Revision Identification Number—RO. 8-bit value that indicates the revision number for the ICH2
7:0 hub interface to PCI bridge. Refer to the Specification Update for the value of the Revision ID
Register.
8-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet