82801BA Datasheet, PDF (160/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.14
General Purpose I/O
Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are
not driven high into powered-down planes.
Some ICH2 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs
are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override
event will result in the ICH2 driving a pin to a logic 1 to another device that is powered down.
SMI# and SCI Routing
The routing bits for GPIO[13:11,8:6,4:3,1:0] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) allow an
input to be routed to SMI# or SCI, or neither. Note that a bit can be routed to either an SMI# or an
SCI, but not both.
Power Wells
GPIO[13:11,8:6,4:3,1] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) have "sticky" bits on the input.
Refer to the GPE1_STS register. As long as the signal goes active for at least 2 clocks, the ICH2
will keep the sticky status bit active. The active level can be selected in the GP_LVL register.
For the 82801BA ICH2, if the system is in an S0 or an S1 state, the GPI inputs are sampled at
33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3–S5 states,
the GPI inputs are sampled at 32.768 KHz, and thus must be active for at least 61 microseconds to
be latched.
For the 82801BAM ICH2-M, if the system is in an S0 state, the GPI inputs are sampled at
33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S1 or S3–S5
states, the GPI inputs are sampled at 32.768 KHz, and thus must be active for at least
61 microseconds to be latched.
If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger
is not required. This makes these signals "level" triggered inputs.
5-98
82801BA ICH2 and 82801BAM ICH2-M Datasheet