82801BA Datasheet, PDF (333/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.11
GPE1_STS—General Purpose Event 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ch
(ACPI GPE1_BLK)
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI
Note: This register is symmetrical to the General Purpose Event 1 Enable Register. GPIOs that are not
implemented will not have the corresponding bits implemented in this register.
Note: Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.
Bit
Description
GPI[15:6] Status (GPI[15:6]_STS)—R/WC.
0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal
is not active. (The status bit cannot be cleared while the corresponding signal is still active).
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).
15:6
If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is
set, then:
- If the system is in an S1_S5 state, the event will also wake the system.
- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will
be generated, depending on the GPI_ROUT bits for the corresponding GPI.
5 Reserved
GPI[4:3] Status (GPI[4:3]_STS)—R/WC.
0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal
is not active. (The status bit cannot be cleared while the corresponding signal is still active).
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).
4:3
If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is
set, then:
- If the system is in an S1_S5 state, the event will also wake the system.
- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will
be generated, depending on the GPI_ROUT bits for the corresponding GPI.
2 Reserved
GPI[1:0] Status (GPI[1:0]_STS)—R/WC.
0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal
is not active. (The status bit cannot be cleared while the corresponding signal is still active).
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).
1:0
If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is
set, then:
- If the system is in an S1_S5 state, the event will also wake the system.
- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be
generated, depending on the GPI_ROUT bits for the corresponding GPI.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-71