82801BA Datasheet, PDF (457/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Electrical Characteristics
Table 16-19. Power Management Timings
Sym
Parameter
Min Max Units
Notes
Fig
t195 SLP_S3# active to SLP_S5# active
1
2 RTCCLK 1, 6
t196
SLP_S3# active to VRMPWRGD (VRMPWRGD
/ VGATE for ICh2-M) inactive
0
ms 5
t196a SLP_S3# active to PWROK
100
us
t197
PWROK, VRMPWRGD inactive to Vcc supplies
inactive
20
ns
t198 Wake Event to SLP_S3#, SLP_S5# inactive
1
20 RTCCLK 1
t198a
(ICH2-M)
Wake Event to SLP_S1# inactive
1
20 RTCCLK
1
t199 SLP_S1# inactive to STP_CPU#, STP_PCI#
(ICH2-M) inactive
3
6
ms
t200 STP_CPU#, STP_PCI# inactive to SUS_STAT#
(ICH2-M) inactive
7
10
ms
t201
(ICH2-M)
SUS_STAT# inactive to CPU_SLP# inactive
2
4 PCICLK
4
t203
(ICH2-M)
STPCLK# inactive to C3_STAT# inactive
0
15
ns
t204
Processor I/F signals latched prior to STPCLK#
active
0
4
CLK66 2
t205 Break Event to STPCLK# inactive
30 3120
ns
t206
STPCLK# inactive to processor I/F signals
unlatched
240 1880
ns
t207
(ICH2-M)
Break Event to STP_CPU# inactive
0
8 PCICLK
4
t208
(ICH2-M)
STP_CPU# inactive to CPU_SLP# inactive
30
45
us
16-25,
16-26
16-25,
16-26
16-25,
16-26
16-25,
16-26
16-25,
16-26
16-23,
16-23,
16-23,
16-23,
16-23,
16-28
16-27
16-27
16-27
16-28
16-28
NOTES:
1. These transitions are clocked off the internal RTC. One RTC clock is approximately 32 us.
2. This transition is clocked off the 66 MHz CLK66. One CLK66 is approximately 15 ns.
3. The ICH2 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
for this cycle getting to the ICH2 is dependant on the processor and the memory controller.
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
5. The ICH2 has no maximum timing requirement for this transition. It is up to the system designer to determine
if the SLP_S3# and SLP_S5# signals are used to control the power planes.
6. If the transition to S5 is due to Power Button Override, SLP_S3# and SLP_S5# are asserted together
following timing t194 (PCIRST# active to SLP_S3# and SLP_S5# active).
7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-17