82801BA Datasheet, PDF (237/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LAN Controller Registers (B1:D8:F0)
7.2.1
System Control Block Status Word Register
Offset Address: 00–01h
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
The ICH2’s integrated LAN Controller places the status of its Command and Receive units and
interrupt indications in this register for the processor to read.
Bit
Description
Command Unit (CU) Executed (CX)—R/WC.
15 ^{1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set.}
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Frame Received (FR)—R/WC.
14 ^{1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame}
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
CU Not Active (CNA)—R/WC.
1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of
the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU
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leaves the Active state and enters either the Idle or the Suspended state. When configured to
generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Receive Not Ready (RNR)—R/WC.
1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU
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Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame
Descriptor.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Management Data Interrupt (MDI)—R/WC.
1 = Set when a Management Data Interface read or write cycle has completed. The management
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data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Software Interrupt (SWI)—R/WC.
10 ^{1 = Set when software generates an interrupt.}
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Early Receive (ER)—R/WC.
9 ^{1 = Indicates the occurrence of an Early Receive Interrupt.}
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Flow control Pause (FCP)—R/WC.
8 ^{1 = Indicates Flow Control Pause interrupt.}
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
Command Unit Status (CUS)—RO.
00 = Idle
7:6 _{01 = Suspended}
10 = LPQ (Low Priority Queue) active
11 = HPQ (High Priority Queue) active
Receive Unit Status (RUS)—RO.
0000 = Idle
0001 = Suspended
0010 = No Resources
5:2 _{0011 = Reserved}
0100 = Ready
0101 = Reserved
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = Suspended with no more RBDs
1010 = No resources due to no more RBDs
1011 = Reserved
1100 = Ready with no RBDs present
1101 = Reserved
1110 = Reserved
1111 = Reserved
1:0 Reserved.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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