82801BA Datasheet, PDF (392/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

SMBus Controller Registers (D31:F3)
12.2.7
12.2.8
12.2.9
BLOCK_DB—Block Data Byte Register
Register Offset: 07h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Block Data Byte—R/W. For Block Writes, software writes the first byte to this register as part of the
setup for this command. After the ICH2 has sent the Address, Command, and Byte Count fields, it will
send the byte in the Block Data Byte register. After the byte has been sent, the ICH2 sets the
BYTE_DONE_STS bit in the Host Status register. If there are more bytes to send, the software then
writes in the next byte to the Block Data Byte register and software also clears the BYTE_DONE_STS
bit. The ICH2 then sends the next byte. During the time from when a byte has been transmitted to
7:0 _{when the next byte has been loaded, the ICH2 inserts wait-states on the SMBus/I}2_C.
A similar process will be used for Block Reads. After receiving the byte count (which goes in the DATA
0 register), the first “data byte” goes in the Block Data Byte register and the ICH2 generates an SMI#
or interrupt (depending on configuration). The interrupt or SMI# handler then reads the byte and
clears the BYTE_DONE_STS bit. This frees room for the next byte. During the time from when a byte
is read to when the BYTE_DONE_STS bit is cleared, the ICH2 inserts wait-states on the SMBus/I²C.
RCV_SLVA—Receive Slave Address Register
Register Offset: 09h
Default Value: 44h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
7
6:0
Description
Reserved
SLAVE_ADDR—R/W. This field is the slave address that the ICH2 decodes for read and write cycles.
The default is not 0 so the SMBus Slave Interface can respond even before the processor comes up
(or if the processor is dead). This register is cleared by RSMRST#, but not by PCIRST#.
SLV_DATA—Receive Slave Data Register
Register Offset: 0Ah
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The CPU can
then read the value from this register. This register is reset by RSMRST#, but not PCIRST#.
Bit
15:8
7:0
Description
DATA_MSG1: Data Message Byte 1—RO. See Section 5.17.5 for a discussion of this field.
DATA_MSG0: Data Message Byte 0—RO. See Section 5.17.5 for a discussion of this field.
12-10
82801BA ICH2 and 82801BAM ICH2-M Datasheet