82801BA Datasheet, PDF (45/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Signal Description
2.11 Processor Interface
Table 2-11. Processor Interface Signals
Name
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
Type
Description
Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h
register, or based on the A20GATE signal.
O
Speed Strap: During the reset sequence, ICH2 drives A20M# high if the
corresponding bit is set in the FREQ_STRP register.
Processor Sleep: This signal puts the processor into a state that saves
O
substantial power compared to Stop-Grant state. However, during that time, no
snoops occur. The ICH2 can optionally assert the CPUSLP# signal when going to
the S1 state.
Numeric Coprocessor Error: This signal is tied to the coprocessor error signal
on the processor. FERR# is only used if the ICH2 coprocessor error reporting
function is enabled in the General Control Register (Device 31:Function 0, Offset
I
D0, bit 13). If FERR# is asserted, the ICH2 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that
IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires
an external weak pull-up to ensure a high level when the coprocessor error
function is disabled.
Ignore Numeric Error: This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the ICH2 coprocessor error reporting function is
enabled in the General Control Register (Device 31:Function 0, Offset D0,
bit 13). If FERR# is active, indicating a coprocessor error, a write to the
O ^{Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE#}
remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
Speed Strap: During the reset sequence, ICH2 drives IGNNE# high if the
corresponding bit is set in the FREQ_STRP register.
Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to reset the
O processor. ICH2 can be configured to support processor BIST. In that case, INIT#
will be active when PCIRST# is active.
Processor Interrupt: INTR is asserted by the ICH2 to signal the processor that
an interrupt request is pending and needs to be serviced. It is an asynchronous
O ^{output and normally driven low.}
Speed Strap: During the reset sequence, ICH2 drives INTR high if the
corresponding bit is set in the FREQ_STRP register.
Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the
processor. The ICH2 can generate an NMI when either SERR# or IOCHK# is
asserted. The processor detects an NMI when it detects a rising edge on NMI.
O ^{NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI}
Status and Control Register.
Speed Strap: During the reset sequence, ICH2 drives NMI high if the
corresponding bit is set in the FREQ_STRP register.
System Management Interrupt: SMI# is an active low output synchronous to
O PCICLK. It is asserted by the ICH2 in response to one of many enabled hardware
or software events.
Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK.
O
It is asserted by the ICH2 in response to one of many hardware or software
events. When the processor samples STPCLK# asserted, it responds by stopping
its internal clock.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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