82801BA Datasheet, PDF (472/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Testability
17.2
Tri-state Mode
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the XOR
Chain outputs.
17.3 XOR Chain Mode
In the ICH2, provisions for Automated Test Equipment (ATE) board level testing are implemented
with XOR Chains. The ICH2 signals are grouped into four independent XOR chains which are
enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within
that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain
(except for the XOR chain’s output) functions as an input. All output and bi-directional buffers for
pins not in the selected XOR chain are tri-stated. Figure 17-2 is a schematic example of XOR chain
circuitry.
Table 17-3 - Table 17-6 list each XOR chain pin ordering, with the first value being the first input
and the last value being the XOR chain output. Table 17-7 lists the signal pins not included in any
XOR chain.
Figure 17-2. Example XOR Chain Circuitry
Vcc
Input
Pin 1
Input
Pin 2
Input
Pin 3
Input
Pin 4
Input
Pin 5
Input
Pin 6
XOR
Chain
Output
17.3.1 XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity (e.g.,
opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 17-2.
Table 17-2. XOR Test Pattern Example
Vector
Input
Pin 1
Input
Pin 2
1
0
0
2
1
0
3
1
1
4
1
1
5
1
1
6
1
1
7
1
1
Input
Pin 3
0
0
0
1
1
1
1
Input
Pin 4
0
0
0
0
1
1
1
Input
Pin 5
0
0
0
0
0
1
1
Input
Pin 6
0
0
0
0
0
0
1
XOR
Output
1
0
1
0
1
0
1
17-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet