82801BA Datasheet, PDF (161/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.15
5.15.1
IDE Controller (D31:F1)
The ICH2 IDE controller features two sets of interface signals (Primary and Secondary) that can be
independently enabled, tri-stated or driven low.
The IDE interfaces of the ICH2 can support several types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not
use the 8237 in the ICH2. This protocol off loads the processor from moving data. This allows
higher transfer rate of up to 16 MB/s.
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 33 MB/s.
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 66 MB/s.
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and
target throttling of data and transfer rates of up to 100 MB/s.
PIO Transfers
The ICH2 IDE controller includes both compatible and fast timing modes. The fast timing modes
can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in
single transaction mode with compatible timings.
Up to 2 IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and
SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the
same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by
programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing
registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are
executed with the synchronous DMA timings. The PIO transfers are executed using compatible
timings or fast timings if also enabled.
PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency:
• Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and
the DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the
DA[2:0] and CSxx# lines prior to assertion of the read and write strobes (DIOR# and
DIOW#).
• Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that transactions may occur back-to-back on the IDE interface
(without incurring startup and shutdown latency) without violating minimum cycle periods for
the IDE interface. The command strobe assertion width for the enhanced timing mode is
selected by the IDETIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time
is selected by the IDETIM Register and may be set to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait states are added to the
command strobe assertion length. If IORDY is negated when the initial sample point is
reached, additional wait states are added. Since the rising edge of IORDY must be
synchronized, at least two additional PCI clocks are added.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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