82801BA Datasheet, PDF (486/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-2. ICH2 Variable I/O Registers (Continued)
Register Name
Offset
EDS Section and Location
BMIDE I/O Registers at BM_BASE + Offset
BM_BASE is set at Section 10.1.10, “BM_BASE—Bus Master Base Address Register (IDE—D31:F1)” on
page 10-4
Command Register Primary
Status Register Primary
00h
Section 10.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 10-11
02h
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 10-12
Descriptor Table Pointer Primary
04h–07h
Section 10.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 10-12
Command Register Secondary
08h
Section 10.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 10-11
Status Register Secondary
0Ah
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 10-12
Descriptor Table Pointer Secondary
0Ch–0Fh
Section 10.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 10-12
USB I/O Registers at Base Address + Offset
USB Base Address is set at Section 11.1.9, “BASE—Base Address Register (USB—D31:F2/F4)” on
page 11-4
USB Command Register
USB Status Register
USB Interrupt Enable
USB Frame Number
USB Frame List Base Address
USB Start of Frame Modify
Port 0, 2 Status/Control
Port 1, 3 Status/Control
Loop Back Test Data
00h–01h
02h–03h
04h–05h
06h–07h
08h–0Bh
0Ch
10h–11h
12h–13h
18h
Section 11.2.1, “USBCMD—USB Command Register”
on page 11-8
Section 11.2.2, “USBSTA—USB Status Register” on
page 11-11
Section 11.2.3, “USBINTR—Interrupt Enable
Register” on page 11-12
Section 11.2.4, “FRNUM—Frame Number Register”
on page 11-12
Section 11.2.5, “FRBASEADD—Frame List Base
Address” on page 11-13
Section 11.2.6, “SOFMOD—Start of Frame Modify
Register” on page 11-13
Section 11.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 11-14
Section 11.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 11-14
SMBus I/O Registers at SMB_BASE + Offset
SMB_BASE is set at Section 12.1.9, “SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)” on
page 12-4
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
00h
Section 12.2.1, “HST_STS—Host Status Register” on
page 12-7
02h
Section 12.2.2, “HST_CNT—Host Control Register”
on page 12-8
03h
Section 12.2.3, “HST_CMD—Host Command
Register” on page 12-9
04h
Section 12.2.4, “XMIT_SLVA—Transmit Slave
Address Register” on page 12-9
05h
Section 12.2.5, “HST_D0—Data 0 Register” on
page 12-9
06h
Section 12.2.6, “HST_D1—Data 1 Register” on
page 12-9
A-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet