82801BA Datasheet, PDF (268/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.10
9.1.11
PMBASE—ACPI Base Address (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
40–43h
00000001h
No
Attribute:
Size:
Usage:
Power Well:
R/W
32-bit
ACPI, Legacy
Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. Can be mapped
anywhere in the 64 KB I/O space on 128-byte boundaries.
Bit
31:16
15:7
6:1
0
Description
Reserved.
Base Address—R/W. Provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is
placed on a 128-byte boundary.
Reserved.
Resource Indicator—RO. Tied to 1 to indicate I/O space.
ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)
Offset Address: 44h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W
8-bit
ACPI, Legacy
Core
Bit
Description
7:5 Reserved.
ACPI Enable (ACPI_EN)—R/W.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power
4
management function is enabled. Note that the APM power management ranges (B2/B3h) are
always enabled and are not affected by this bit.
0 = Disable.
3 Reserved.
SCI IRQ Select (SCI_IRQ_SEL)—R/W. Specifies on which IRQ the SCI will internally appear. If not
using the APIC, the SCI must be routed to IRQ[9:11], and that interrupt is not sharable with the
SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ[20:23], and can be shared with other interrupts.
000 = IRQ9
001 = IRQ10
2:0 _{010 = IRQ11}
011 = Reserved
100 = IRQ20 (Only available if APIC enabled)
101 = IRQ21 (Only available if APIC enabled)
110 = RQ22 (Only available if APIC enabled)
111 = IRQ23 (Only available if APIC enabled)
9-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet