82801BA Datasheet, PDF (153/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.11.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written for the PIC to operate
properly. Therefore, there is no need to return these values in alternate access mode. When reading
PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-49.
Table 5-49. PIC Reserved Bits Return Values
PIC Reserved Bits
Value Returned
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
OCW2(4:3)
OCW3(7)
OCW3(5)
OCW3(4:3)
000
000
00
0
00
0
Reflects bit 6
01
5.12.11.3 Read Only Registers with Write Paths in Alternate Access Mode
The registers described in Table 5-50 have write paths alternate access mode. Software restores
these values after returning from a powered down state. These registers must be handled specially
by software. When in normal mode, writing to the Base Address and Count Register also writes to
the Current Address and Count Register. Therefore, the Base Address and Count must be written
first, then the part is put into alternate access mode and the Current Address and Count Register is
written.
Table 5-50. Register Write Accesses in Alternate Access Mode
I/O Address
Register Write Value
08h
DMA Status Register for channels 0–3.
D0h
DMA Status Register for channels 4–7.
5.12.12 System Power Supplies, Planes, and Signals
Power Plane Control with SLP_S3# and SLP_S5#
The SLP_S3# output signal can be used to cut power to the system core supply, since it will only go
active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH2
Resume Well, and to any other circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard. The SLP_S5# output signal can be used to cut power to the system core supply, as
well as power to the system memory, since the context of the system is saved on the disk. Cutting
power to the memory may be done via the power supply, or by external FETs to the motherboard.
SLP_S1# Signal (82801BAM ICH2-M)
For the ICH2-M, the SLP_S1# output signal will typically be connected to the clock synthesizer’s
PWRDWN# input to stop the clock synthesizer’s PLL. Alternative implementations may use this
signal to cut power to non-critical subsystems while in the S1 state.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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