82801BA Datasheet, PDF (254/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.10
8.1.11
8.1.12
8.1.13
PBUS_NUM—Primary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Primary Bus Number—RO. This field indicates the bus number of the hub interface and is hardwired
to 00h.
SBUS_NUM—Secondary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 19h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Secondary Bus Number—R/W. This field indicates the bus number of PCI. Note that when this
7:0 number is equal to the primary bus number (i.e., bus #0), the ICH2 will run hub interface configuration
cycles to this bus number as Type 1 configuration cycles on PCI.
SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 1A
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Subordinate Bus Number—R/W. This field specifies the highest PCI bus number below the hub
7:0
interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the
Secondary-to-Subordinate Bus ranges of Device 30, the ICH2 indicates a master abort back to the
hub interface.
SMLT—Secondary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This Master Latency Timer (MLT) controls the amount of time that the ICH2 continues to burst
data as a master on the PCI bus. When the ICH2 starts the cycle after being granted the bus, the
counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to
this device is removed, then the expiration of the MLT counter results in the deassertion of
FRAME#. If the internal grant has not been removed, the ICH2 can continue to own the bus.
Bit
Description
7:3
Master Latency Count—R/W. This 5-bit value indicates the number of PCI clocks, in 8-clock
increments, that the ICH2 remains as master of the bus.
2:0 Reserved.
8-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet