82801BA Datasheet, PDF (422/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Modem Controller Registers (D31:F6)
14.2.8
Bit
Description
Run/Pause Bus master (RPBM)—R/W.
0
0 = Pause bus master operation. This results in all state information being retained (i.e., master
mode operation can be stopped and then resumed).
1 = Run. Bus master operation starts.
GLOB_CNT—Global Control Register
I/O Address:
Default Value:
Lockable:
MBAR + 3Ch
00000000h
No
Attribute:
Size:
Power Well:
This register can be accessed only as a DWord (32 bits).
R/W (DWord access only)
32 bits
Core
Bit
31:6
5
4
3
2
1
0
Description
Reserved.
Secondary Resume Interrupt Enable—R/W.
0 = Disable.
1 = Enable an interrupt to occur when the secondary codec causes a resume event on the
AC-link.
Primary Resume Interrupt Enable—R/W.
0 = Disable.
1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link.
ACLINK Shut Off—R/W.
0 = Normal operation.
1 = Disable the AC-link signals (drive all AC’97 outputs low and turn off all AC’97 input buffer
enables)
AC’97 Warm Reset—R/W (special).
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken
a suspended codec without clearing its internal registers. If software attempts to perform a
warm reset while BIT_CLK is running, the write will be ignored and the bit will not be changed.
A warm reset can only occur in the absence of BIT_CLK.
0 = This bit is self-clearing (it clears itself after the reset has occurred and BIT_CLK has started).
AC‘97 Cold Reset#—R/W (special).
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC‘97 circuitry. All data in the
codec will be lost. Software needs to clear this bit no sooner than after 1usec has elapsed.
This bit reflects the state of the AC_RST# pin. The ICH2 clears this bit to “0” upon entering
S3/S4/S5 sleep states and PCIRST#.
GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI
causes an interrupt.
0 = Bit 0 of the Global Status Register is set, but an interrupt is not generated.
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
14-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet