82801BA Datasheet, PDF (57/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Power Planes and Pin States
Table 3-4. Power Plane and States for Output and I/O Signals (Continued)
Signal Name
Power
Plane
Reset Signal
During Reset
Immediately
after Reset
C3
(ICH2-M)
S1
S3
S4/S5
SMBus Interface
SMBCLK, SMBDATA Resume I/O RSMRST#
High-Z
High-Z
Defined
Defined
Defined Defined
System Management Interface
SMLINK[1:0]
Resume I/O RSMRST#
High-Z
High-Z
Defined
Defined
Defined Defined
Miscellaneous Signals
SPKR
Main I/O
PCIRST#
High-Z with
internal pull-up
Low
Defined
Defined
Off
Off
AC’97 Interface
AC_RST#
Resume I/O RSMRST#
Low
AC_SDOUT
Main I/O
PCIRST#
Low
AC_SYNC
Main I/O
PCIRST#
Low
Low
High
Cold Reset Bit
(High)
Low
Low
Running
Running
Low
Off
Off
Running
Running
Low
Off
Off
Unmuxed GPIO Signals
GPIO[18] (ICH2)
Main I/O
PCIRST#
High
See Note 2
—
Defined
Off
Off
GPIO[19:20] (ICH2)
Main I/O
PCIRST#
High
High
—
Defined
Off
Off
GPIO[21] (ICH2)
Main I/O
PCIRST#
High
High
—
Defined
Off
Off
GPIO[22] (ICH2)
Main I/O
PCIRST#
High-Z
High-Z
—
Defined
Off
Off
GPIO[23] (ICH2)
Main I/O
PCIRST#
Low
Low
—
Defined
Off
Off
GPIO[24] (ICH2)
Resume I/O RSMRST#
High-Z
High
—
Defined
Defined Defined
GPIO[25]
Resume I/O RSMRST#
High-Z
High
Defined
Defined
Defined Defined
GPIO[27:28]
.
Resume I/O
RSMRST#
HIgh-Z
High
Defined
Defined
Defined Defined
NOTES:
1. ICH2 and ICH2-M: The ICH2/ICH2-M sets these signals at reset for processor frequency strap.
2. ICH2 and ICH2-M: GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH2 comes out of reset
3. ICH2 and ICH2-M: CPUPWRGD is an open-drain output that represents a logical AND of the ICH2’s VRMPWRGD
(VGATE / VRMPWRGD for the ICH2-M) and PWROK signals and, thus, are driven low by ICH2/ICH2-M when either
VRMPWRGD (VGATE / VRMPWRGD for the ICH2-M) or PWROK are inactive. During boot, or during a hard reset with power
cycling, CPUPWRGD will be expected to transition from low to High-Z.
4. ICH2-M Only: LAN Connect and EEPROM signals will either be "Defined" or "Off" in S3–S5 states depending on whether or
not the LAN power planes are active.
5. GPIO[24:25, 27:28] for the ICH2 and GPIO[25, 27:28] for the 82801BAM ICH2-M: These signals remain tri-stated for up to
110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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