82801BA Datasheet, PDF (301/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.4.10
ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: 4D0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat
timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit
IRQ7 ECL—R/W.
7 _{0 = Edge.}
1 = Level.
IRQ6 ECL—R/W.
6 _{0 = Edge.}
1 = Level.
IRQ5 ECL—R/W.
5 _{0 = Edge.}
1 = Level.
IRQ4 ECL—R/W.
4 _{0 = Edge.}
1 = Level.
IRQ3 ECL—R/W.
3 _{0 = Edge.}
1 = Level.
2:0 Reserved. Must be 0.
Description
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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