82801BA Datasheet, PDF (283/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.34
FWH_DEC_EN2—FWH Decode Enable 2 Register
(LPC I/F—D31:F0)
Offset Address: F0h
Default Value: 0Fh
Attribute:
Size:
R/W
8 bits
This register determines which memory ranges are decoded on the PCI bus and forwarded to the
FWH. The ICH2 subtractively decodes cycles on PCI unless POS_DEC_EN is set to 1.
Bit
Description
7:4 Reserved.
FWH Address Range Enable (FWH_70_EN)—R/W. Enables decoding two 1 MB FWH memory
ranges.
3
0 = Disable.
1 = Enable the following ranges for the FWH
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FWH Address Range Enable (FWH_60_EN)—R/W. Enables decoding two 1 MB FWH memory
ranges.
2
0 = Disable.
1 = Enable the following ranges for the FWH
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FWH Address Range Enable (FWH_50_EN)—R/W. Enables decoding two 1 MB FWH memory
ranges.
1
0 = Disable.
1 = Enable the following ranges for the FWH
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FWH Address Range Enable (FWH_40_EN)—R/W. Enables decoding two 1 MB FWH memory
ranges.
0
0 = Disable.
1 = Enable the following ranges for the FWH
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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