82801BA Datasheet, PDF (142/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.6.4
5.12.6.5
Conditions for Re-Starting the PCI Clock (82801BAM ICH2-M)
Behavioral Description
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH2-M observes the CLKRUN# signal asserted for 1 (free running) clock, the
ICH2-M deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running)
clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH2-M
again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the ICH2-M re-asserts CLKRUN#, and
simultaneously deasserts the STP_PCI# signal.
Other Causes of CLKRUN# Going Active (82801BAM ICH2-M)
The following causes the ICH2-M to assert and/or maintain the CLKRUN# signal active (low):
• PC/PCI activity, which is started by one of the REQx# signals going active. It is expected that
a PC/PCI device asserts CLKRUN# prior to starting the start bit on the REQ# signal. Once the
start bit is recognized, the ICH2-M makes sure CLKRUN# goes active if it should go inactive
during the sequence.
• SERIRQ activity, which is started by the SERIRQ signal going low (in Quiet mode), or the
SERIRQ logic being in the Continuous Mode. It is expected that a SERIRQ device asserts
CLKRUN# prior to starting the start bit on the SEIRQ signal. Once the start bit is recognized,
the ICH2-M makes sure CLKRUN# goes active if it should go inactive during the sequence.
• Any internal or external bus master request, including LPC masters. Once the master request
is detected (via PCI REQ or LPC LDRQ[1:0]#), the ICH2-M maintains CLKRUN# active
until the end of the sequence. This includes:
— Any PCI REQ# low
— Bus Master or DMA request pending (having come in via LDRQ[1:0]#)
— Any cycle coming down from hub interface1 to PCI
— Any PCI cycle currently in progress. For example, cycle forward by the ICH2-M from
the hub interface to PCI, and then claimed by ICH2-M's PCI-to-LPC logic. That cycle
runs as a Delayed Transaction on PCI. CLKRUN# should stay low until the cycle
completes (without Delayed Transaction).
• Any bus master below PCI that needs to run a cycle. This could include the Front-Side-Bus
interrupt logic for the I/O APIC (if it is downstream of PCI).
5.12.6.6
LPC Devices and CLKRUN# (82801BAM ICH2-M)
If an LPC device (of any type) needs the 33 MHz PCI clock (e.g., for LPC DMA or LPC serial
interrupt), it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles do
not need to assert CLKRUN#, since the ICH2-M asserts it on their behalf.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet