82801BA Datasheet, PDF (390/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

SMBus Controller Registers (D31:F3)
12.2.2
HST_CNT—Host Control Register
Register Offset: 02h
Default Value: 00h
Attribute:
Size:
R/W
8-bits
Bit
Description
7 Reserved.
START—WO.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers
6
should be setup prior to writing a 1 to this bit position.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset
00h) can be used to identify when the ICH2 has finished the command.
LAST BYTE—WO. This bit is used for Block Read commands.
5 1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the
block. This causes the ICH2 to send a NACK (instead of an ACK) after receiving the last byte.
SMBus Command (SMB_CMD)—R/W. The bit encoding below indicates which command the ICH2
is to perform. If enabled, the ICH2 generates an interrupt or SMI# when the command has
completed. If the value is for a non-supported or reserved command, the ICH2 sets the device error
(DEV_ERR) status bit and generates an interrupt when the START bit is set. The ICH2 performs no
command and does not operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address
register.
001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the
slave address register determines if this is a read or write command.
010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers.
Bit 0 of the slave address register determines if this is a read or write command. If it is a read,
the DATA0 register will contain the read data.
011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command. If it
4:2
is a read, after the command completes, the DATA0 and DATA1 registers will contain the read
data.
100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1
registers. Bit 0 of the slave address register determines if this is a read or write command.
After the command completes, the DATA0 and DATA1 registers will contain the read data.
101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the
Block Data Byte register. For block write, the count is stored in the DATA0 register and
indicates how many bytes of data will be transferred. For block reads, the count is received
and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or
write command. For writes, data is retrieved from the first n (where n is equal to the specified
count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte
register.
110 = I²C Read: This command uses the transmit slave address, command, DATA0, DATA1
registers, and the Block Data Byte register. The read data is stored in the Block Data Byte
register. The ICH2 will continue reading data until the NAK is received.
111 = Reserved
KILL—R/W.
1 = When set, kills the current host transaction taking place, sets the FAILED status bit, and
1
asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the
SMBus Host Controller to function normally.
0 = Normal SMBus Host Controller functionality.
INTREN—R/W.
0
1 = Enable the generation of an interrupt or SMI# upon the completion of the command.
0 = Disable.
12-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet