82801BA Datasheet, PDF (355/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
IDE Controller Registers (D31:F1) 10
10.1 PCI Configuration Registers (IDE—D31:F1)
Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
All of the IDE registers are in the Core well. None can be locked.
Table 10-1. PCI Configuration Map (IDE—D31:F1)
Offset
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
20h–23h
2C–2Dh
Mnemonic
VID
DID
CMD
STS
RID
PI
SCC
BCC
MLT
HTYPE
BAR
SVID
Register Name/Function
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Header Type
Base Address Register
Subsystem Vendor ID
2E–2Fh
40h–41h
42–43h
44h
48h
4Ah–4Bh
54h
SID
Subsystem ID
IDE_TIMP
ID_TIMS
SIDETIM
SDMAC
SDMATIM
IDE_CONFIG
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control Register
Synchronous DMA Timing Register
IDE I/O Configuration Register
Default
8086h
244Bh (ICH2)
244Ah (ICH2-M)
00h
0280h
See Note 1
80h
01h
01h
00
00h
00000001h
00
00
0000h
0000h
00h
00h
0000h
00h
Type
RO
RO
R/W
R/W
RO
RO
RO
RO
RO
RO
R/W
R/Write-
Once
R/Write-
Once
R/W
R/W
R/W
R/W
R/W
R/W
NOTES:
1. Refer to the Specification Update for the value of the Revision ID Register
2. The ICH2 IDE controller is not arbitrated as a PCI device; therefore, it doe s not need a master latency timer.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-1