82801BA Datasheet, PDF (369/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
11.1.4
11.1.5
11.1.6
STA—Device Status Register (USB—D31:F2/F4)
Address Offset:
Default Value:
06–07h
0280h
Attribute:
Size:
R/WC
16 bits
Bit
Description
15:14 Reserved as ‘00b’. Read Only.
Received Master-Abort Status (RMA)—R/WC.
13 ^{1 = USB, as a master, generated a master-abort.}
0 = Software clears this bit by writing a 1 to the bit location.
12 Reserved. Always read as 0.
Signaled Target-Abort Status (STA)—R/WC.
11 1 = USB function is targeted with a transaction that the ICH2 terminates with a target abort.
0 = Software clears this bit by writing a 1 to the bit location.
DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion.
10:9 These read only bits indicate the ICH2's DEVSEL# timing when performing a positive decode. ICH2
generates DEVSEL# with medium timing for USB.
8 Data Parity Error Detected: Reserved as 0. Read Only.
7 Fast Back-to-Back Capable: Reserved as 1. Read Only.
6 User Definable Features (UDF): Reserved as 0. Read Only.
5 66 MHz Capable: Reserved as 0. Read Only.
4:0 Reserved.
RID—Revision Identification Register (USB—D31:F2/F4)
Address Offset:
Default Value:
08h
See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification. These bits contain device stepping information and are hardwired to the
default value. Refer to the Specification Update for the value of the Revision ID Register.
PI—Programming Interface (USB—D31:F2/F4)
Address Offset:
09h
Default Value:
00h
Attribute:
Size:
RO
8 bits
Bit
Description
Programming Interface—RO.
7:0
00h = No specific register level programming interface defined.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
11-3