82801BA Datasheet, PDF (274/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Bit
Description
Mouse IRQ12 Latch Enable (IRQ12LEN)—R/W.
11 ^{1 = The active edge of IRQ12 will be latched and held until a port 60h read.}
0 = IRQ12 will bypass the latch.
10:9 Reserved
APIC Enable (APIC_EN)—R/W.
8^{1 1 = Enables the internal I/O (x) APIC and its address decode.}
0 = Disables internal I/O (x) APIC.
Enables I/O (x) Extension Enable (XAPIC_EN)—R/W. Note that this bit is only valid if the
AIPC_EN bit (bit 8) is also set to 1.
7¹
1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC.
0 = The I/O (x) APIC extensions are not supported.
Alternate Access Mode Enable (ALTACC_EN)—R/W.
1 = Alternate Access Mode Enable
6
0 = Alternate Access Mode Disabled (default). Alternate Access Mode allows reads to otherwise
unreadable registers and writes otherwise unwriteable registers.
5:3 Reserved.
DMA Collection Buffer Enable (DCB_EN)—R/W.
2
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.
0 = DCB disabled.
Delayed Transaction Enable (DTE)—R/W.
1
1 = ICH2 enables delayed transactions for internal register, FWH, and LPC interface accesses.
0 = Delayed transactions disabled.
Positive Decode Enable (POS_DEC_EN)—R/W.
1 = Enables ICH2 to only perform positive decode on the PCI bus.
0
0 = The ICH2 performs subtractive decode on the PCI bus and forward the cycles to LPC interface
if not to an internal register or other known target on the LPC interface. Accesses to internal
registers and to known LPC interface devices are still be positively decoded.
NOTES:
1. Rule 1: If bit 8 is 0, the ICH2 does not decode any of the registers associated with the I/O APIC or I/O (x)
APIC. The state of bit 7 is a “Don’t Care” in this case.
Rule 2: If bit 8 is 1 and bit 7 is 0, the ICH2 decodes the memory space associated with the I/O APIC, but not
the extra registers associated with the I/O (x) APIC.
Rule 3: If bit 8 is 1 and bit 7 is 1, the ICH2 decodes the memory space associated with both the I/O APIC and
the I/O (x) APIC. This also enables PCI masters to write directly to the register to cause interrupts (PCI
Message Interrupt).
Note that there is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled. This is
not considered necessary.
9-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet