82801BA Datasheet, PDF(83/498 Page) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

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82801BA Datasheet, PDF (83/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

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Functional Description

5.3.1 LPC Interface

The ICH2 implements an LPC interface as described in the LPC 1.0 specification. The LPC

interface to the ICH2 is shown in Figure 5-6. Note that the ICH2 implements all of the signals that

are shown as optional, but peripherals are not required to do so.

Figure 5-6. LPC Interface Diagram

PCI Bus

IICCHH2

SUS_STAT#

GPI

LAD[3:0]

LFRAME#

LDRQ#

(optional)

LPCPD#

(optional)

LSMI#

(optional)

PCI PCI

CLK RST#

PCI

PCI

SERIRQ PME#

Super I/O

5.3.1.1 LPC Cycle Types

The ICH2 implements all of the cycle types described in the LPC I/F 1.0 specification. Table 5-3

shows the cycle types supported by the ICH2.

Table 5-3. LPC Cycle Types Supported

Cycle Type

Comment

Memory Read

Memory Write

I/O Read

I/O Write

DMA Read

DMA Write

Bus Master Read

Bus Master Write

Single: 1 byte only

Single: 1 byte only

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

Can be 1 or 2 bytes

Can be 1 or 2 bytes

Can be 1, 2, or 4 bytes. (See Note 2 below)

Can be 1, 2, or 4 bytes. (See Note 2 below)

NOTES:

1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH2will perform standard

LPC memory cycles. It will only attempt 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will

appear as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI,

it will appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be

subsequently aborted, and the ICH2 will return a value of all 1s to the processor. This is done to maintain

compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any

address. However, the 2-byte transfer must be word aligned (i.e. with an address where A0=0). A DWord

transfer must be DWord aligned (i.e., with an address where A1and A0 are both 0)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-21

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