82801BA Datasheet, PDF (347/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10 General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte I/O space.
The base offset for this space is selected by the GPIO_BAR register. Table 9-12 summarizes the
ICH2 GPIO implementation.
Table 9-12. Summary of GPIO Implementation
GPIO
Type
Alternate
Function
(Note 1)
Power
Well
Notes
GPIO[0]
Input
Only
REQ[A]#
GPIO[1]
Input REQ[B]# or
Only
REQ[5]#
GPIO[2]
GPIO[3:4]
GPIO[5]
N/A
Input
Only
N/A
N/A
PIRQ[E:H]#
N/A
GPIO[6]
Input
Only
Unmuxed
GPIO[7]
GPIO[8]
GPIO[9:10]
Input
Only
Input
Only
N/A
Unmuxed
Unmuxed
N/A
GPIO[11]
Input
Only
SMBALERT#
GPIO[12]
Input
Only
GPIO[13]
Input
Only
GPIO[14:15] N/A
GPIO[16]
Output
Only
GPIO[17]
Output
Only
Unmuxed
Unmuxed
N/A
GNT[A]#
GNT[B]# or
GNT[5]#
GPIO[18:19]
Output
Only
Unmuxed
Core
Core
N/A
Core
N/A
Core
Core
Resume
N/A
Resume
Resume
Resume
N/A
Core
Core
Core
GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair.
Input active status read from GPE1_STS register bit 0.
Input active high/low set through GPI_INV register bit 0.
GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair
(See note 4).
Input active status read from GPE1_STS register bit 1.
Input active high/low set through GPI_INV register bit 1.
Not implemented
GPIO_USE_SEL bits [3:4] enable PIRQ[F:G]#.
Input active status read from GPE1_STS reg. bits [3:4].
Input active high/low set through GPI_INV reg. bit [3:4].
Not implemented
ICH2 (82801BA):
Input active status read from GPE1_STS register bit 6.
Input active high/low set through GPI_INV register bit 6.
ICH2-M (82801BAM):
Not implemented.
Input active status read from GPE1_STS register bit 7.
Input active high/low set through GPI_INV register bit 7
Input active status read from GPE1_STS register bit 8.
Input active high/low set through GPI_INV register bit 8.
Not implemented
GPIO_USE_SEL bit 11 enables SMBALERT#
Input active status read from GPE1_STS register bit 11.
Input active high/low set through GPI_INV register bit 11.
Input active status read from GPE1_STS register bit 12.
Input active high/low set through GPI_INV register bit 12.
Input active status read from GPE1_STS register bit 13.
Input active high/low set through GPI_INV register bit 13.
Not Implemented
Output controlled via GP_LVL register bit 16.
TTL driver output
Output controlled via GP_LVL register bit 17.
TTL driver output
ICH2 (82801BA):
Output controlled via GP_LVL register bits [18:19].
TTL driver output
ICH2-M (82801BAM):
Not implemented.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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