82801BA Datasheet, PDF (41/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Signal Description
2.6
IDE Interface
Table 2-6. IDE Interface Signals
Name
PDCS1#,
SDCS1#
PDCS3#,
SDCS3#
PDA[2:0],
SDA[2:0]
PDD[15:0],
SDD[15:0]
PDDREQ,
SDDREQ
PDDACK#,
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY
Type
Description
Primary and Secondary IDE Device Chip Selects for 100 Range: These
O signals are for the ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Chip Select for 300 Range: These signals
O are for the ATA control register block. This output signal is connected to the
corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Address: These output signals are
O
connected to the corresponding signals on the primary or secondary IDE
connectors. They are used to indicate which byte in either the ATA command
block or control block is being addressed.
Primary and Secondary IDE Device Data: These signals directly drive the
I/O corresponding signals on the primary or secondary IDE connector. There is a
weak internal pull-down resistor on PDD[7] and SDD[7].
Primary and Secondary IDE Device DMA Request: These input signals are
directly driven from the DRQ signals on the primary or secondary IDE connector.
I
It is asserted by the IDE device to request a data transfer, and used in
conjunction with the PCI bus master IDE function. They are not associated with
any AT-compatible DMA channel. There is a weak internal pull-down resistor on
these signals.
Primary and Secondary IDE Device DMA Acknowledge: These signals
directly drive the DAK# signals on the primary and secondary IDE connectors.
O
Each signal is asserted by the ICH2 to indicate to the IDE DMA slave devices that
a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer
cycle. This signal is used in conjunction with the PCI bus master IDE function and
are not associated with any AT-compatible DMA channel.
Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may drive data on the PDD or SDD lines. Data
is latched by the ICH2 on the deassertion edge of PDIOR# or SDIOR#. The IDE
device is selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
acknowledge (PDDAK# or SDDAK#).
O _{Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is}
the data write strobe for writes to disk. When writing to disk, ICH2 drives valid
data on rising and falling edges of PDWSTB or SDWSTB.
Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This
is the DMA ready for reads from disk. When reading from disk, ICH2 deasserts
PRDMARDY# or SRDMARDY# to pause burst data transfers.
Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may latch data from the PDD or SDD lines.
Data is latched by the IDE device on the deassertion edge of PDIOW# or
SDIOW#. The IDE device is selected either by the ATA register file chip selects
O _{(PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the}
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): ICH2 asserts this signal to
terminate a burst.
Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe
active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than
the minimum width. It adds wait states to PIO transfers.
I
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk):
When reading from disk, ICH2 latches data on rising and falling edges of this
signal from the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When
writing to disk, this is deasserted by the disk to pause burst data transfers.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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