82801BA Datasheet, PDF (68/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.1.7
5.2
PCI Dual Address Cycle (DAC) Support
(82801BA ICH2 only)
The 82801BA ICH2 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI
initiators to main memory. This allows PCI masters to generate an address up to 44 bits. The size
of the actual supported memory space will be determined by the memory controller and the
processor.
The DAC mode is only supported for PCI adapters and is not supported for any of the internal PCI
masters (IDE, LAN, USB, AC’97, 8237 DMA, etc.). ICH2 does not support DAC for processor-
initiated cycles.
When a PCI master wants to initiate a cycle with an address above 4 GB, it follows the following
behavioral rules (See PCI 2.2 Specification, section 3.9 for more details):
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC
encoding on the C/BE# signals. This unique encoding is 1101.
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address.
3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is
right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0,
however the ICH2 will ignore these bits. C/BE# indicate the bus command type (Memory
Read, Memory Write, etc.)
4. The rest of the cycle proceeds normally.
LAN Controller (B1:D8:F0)
The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high
level commands and perform multiple operations, which lowers processor utilization by off-
loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB
each help prevent data underruns and overruns while waiting for bus accesses. This enables the
integrated LAN Controller to transmit data with minimum interframe spacing (IFS).
The ICH2 integrated LAN Controller can operate in either full duplex or half duplex mode. In full
duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
The integrated LAN Controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration parameters.
From a software perspective, the integrated LAN Controller appears to reside on the secondary side
of the ICH2’s virtual PCI-to-PCI Bridge (see Section 5.1.2). This is typically Bus 1; it may be
assigned a different number depending on system configuration.
5-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet