82801BA Datasheet, PDF (372/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
11.1.15
USB_LEGKEY—USB Legacy Keyboard/Mouse Control
Register (USB—D31:F2/F4)
Address Offset:
Default Value:
C0–C1
2000h
Attribute:
Size:
R/W, R/WC, RO
16 bits
Bit
Description
SMI Caused by End of Pass-through (SMIBYENDPS)—R/WC. Indicates if the event occurred.
Note that even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the
15 ^{SMM code to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software clears this bit by writing a 1 to the bit location.
14 Reserved.
PCI Interrupt Enable (USBPIRQEN)—R/W. Used to prevent the USB controller from generating an
interrupt due to transactions on its ports. Note that it will probably be configured to generate an SMI
13 ^{using bit 4 of this register. Default to 1 for compatibility with older USB software.}
1 = Enable
0 = Disable
SMI Caused by USB Interrupt (SMIBYUSB)—RO. Indicates if the event occurred. Note that even if
the corresponding enable bit is not set in the bit 4, this bit will still be active. It is up to the SMM code
12 ^{to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software should clear the IRQ via the USB controller. Writing a 1 to this bit will have no effect.
SMI Caused by Port 64 Write (TRAPBY64W)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM
11 ^{code to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software clears this bit by writing a 1 to the bit location.
SMI Caused by Port 64 Read (TRAPBY64R)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM
10 ^{code to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software clears this bit by writing a 1 to the bit location.
SMI Caused by Port 60 Write (TRAPBY60W)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM
9 ^{code to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software clears this bit by writing a 1 to the bit location.
SMI Caused by Port 60 Read (TRAPBY60R)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the SMM
8 ^{code to use the enable bit to determine the exact cause of the SMI#.}
1 = Event Occurred
0 = Software clears this bit by writing a 1 to the bit location.
SMI at End of Pass-through Enable (SMIATENDPS)—R/W. May need to cause SMI at the end of a
pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be
7 ^{serviced later.}
1 = Enable
0 = Disable
Pass Through State (PSTATE)—RO.
6 ^{1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.}
0 = If software needs to reset this bit, it should set bit 5 to 0.
A20Gate Pass-Through Enable (A20PASSEN)—R/W.
1 = Allows A20GATE sequence Pass-Through function. SMI# will not be generated, even if the
5
various enable bits are set.
0 = Disable
11-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet