82801BA Datasheet, PDF (224/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Register and Memory Mapping
6.4
Memory Map
Table 6-4 shows (from the processor perspective) the memory ranges that the ICH2 decodes.
Cycles that arrive from the MCH will first be driven out on PCI. The ICH2 may then claim the
cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is
enabled, the cycle can be forwarded to LPC.
PCI cycles generated by an external PCI master will be positively decoded unless it falls in the
PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If the
cycle is not in the I/O APIC or LPC ranges, it will be forwarded up the hub interface to the Host
Controller.
Table 6-4. Memory Decode Ranges from Processor Perspective
Memory Range
Target
Dependency/Comments
0000 0000h–000D FFFFh
0010 0000–TOM (Top of
Memory)
000E 0000h–000F FFFFh
Main Memory
FWH
TOM registers in Host Controller
Bit 7 in FWH Decode Enable Register is set
FEC0 0000h–FEC0 0100h I/O APIC inside ICH2
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FWH
Bit 0 in FWH Decode Enable Register
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
FWH
FWH
Bit 1 in FWH Decode Enable Register
Bit 2 in FWH Decode Enable Register is set
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
FWH
Bit 3 in FWH Decode Enable Register is set
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FWH
Bit 4 in FWH Decode Enable Register is set
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FWH
Bit 5 in FWH Decode Enable Register is set
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FWH
FWH
Bit 6 in FWH Decode Enable Register is set.
Always enabled.
The top two 64 KB blocks of this range can be
swapped as described in Section 6.4.1.
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FWH
Bit 3 in FWH Decode Enable 2 Register is set
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FWH
FWH
Bit 2 in FWH Decode Enable 2 Register is set
Bit 1 in FWH Decode Enable 2 Register is set
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
FWH
Bit 0 in FWH Decode Enable 2 Register is set
Anywhere in 4 GB range
D110 LAN Controller
Enable via BAR in Device 29:Function 0 (D110 LAN
Controller)
All other
PCI
None
6-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet