82801BA Datasheet, PDF (97/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.5.10
5.5.11
5.5.12
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the host has
won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F
and begins the DMA transfer. The general flow for a basic DMA transfer is as follows:
1. ICH2 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. ICH2 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. ICH2 asserts channel number and, if applicable, terminal count.
4. ICH2 indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read,
— The ICH2 drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16 bit transfer, the process is repeated for the next 8 bits.
6. If a DMA write,
— The ICH2 turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16 bit transfer, the peripheral indicates data ready and transfers the next byte.
7. The peripheral turns around the bus.
Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last
byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, this is the last byte.
On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, the second byte is the last byte.
Therefore, the peripheral must internalize the TC bit when the CHANNEL field is communicated
and only signal TC when the last byte of that transfer size has been transferred.
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a
DMA write where the peripheral is transferring data to main memory. The indication from the host
is the same as a DMA write, so the peripheral will be driving data onto the LPC interface.
However, the host does not transfer this data into main memory.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-35