82801BA Datasheet, PDF (348/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Table 9-12. Summary of GPIO Implementation (Continued)
GPIO
Type
Alternate
Function
(Note 1)
GPIO[20]
Output
Only
Unmuxed
GPIO[21]
Output
Only
Unmuxed for
ICH2
82801BA
CS_STAT#
for ICH2-M
82801BAM
GPIO[22]
Output
Only
Unmuxed
GPIO[23]
Output
Only
Unmuxed
GPIO[24]
Input /
Output
Unmuxed
GPIO[25]
Input /
Output
Unmuxed
GPIO[26] N/A
GPIO[27:28]
Input /
Output
GPIO[29:31] N/A
N/A
Unmuxed
N/A
Power
Well
Notes
Core
ICH2 (82801BA):
Output controlled via GP_LVL register bit 20.
TTL driver output
ICH2-M (82801BAM):
Not implemented.
Core
ICH2 (82801BA):
This GPO defaults high.
Output controlled via GP_LVL register bit 21.
TTL driver output
ICH2-M (82801BAM):
Output controlled via GP_LVL register bit 21.
TTL driver output
Core
ICH2 (82801BA):
Output controlled via GP_LVL register bit [22].
Open-drain output
ICH2-M (82801BAM):
Not implemented.
Core
ICH2 (82801BA):
Output controlled via GP_LVL register bit [23].
TTL driver output
ICH2-M (82801BAM):
Not implemented.
Resume
ICH2 (82801BA):
Input active status read from GP_LVL register bit 24.
Output controlled via GP_LVL register bit 24.
TTL driver output
ICH2-M (82801BAM):
Not implemented.
Resume
Blink enabled via GPO_BLINK register bit 25.
Input active status read from GP_LVL register bit 25
Output controlled via GP_LVL register bit 25.
TTL driver output
N/A Not implemented
Input active status read from GP_LVL register bits [27:28]
Resume Output controlled via GP_LVL register bits [27:28]
TTL driver output
N/A Not implemented
NOTES:
1. All GPIOs default to their alternate function
2. All inputs are sticky. The status bit will remain set as long as the input was asserted for 2 clocks. GPIs are
sampled on PCI clocks in S0/S1...
3. GPIs are sampled on RTC clocks in S3/S4/S5 for the 82801BA ICH2 and in S1/S3/S4/S5 for the 82801BAM
ICH2-M.
4. GPIO[7:6,4:3,1:0] (GPIO[7,4:3,1:0] for the ICH2-M) are 5V tolerant, and all GPIs can be routed to cause an
SCI or SMI#
5. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See
Section 9.1.22.
9-86
82801BA ICH2 and 82801BAM ICH2-M Datasheet