82801BA Datasheet, PDF (389/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

SMBus Controller Registers (D31:F3)
12.2.1
HST_STS—Host Status Register
Register Offset: 00h
Default Value: 00h
Attribute:
Size:
R/WC
8-bits
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position. Writing a zero to any bit position has no effect.
Bit
Description
Byte Done Status (BYTE_DONE_STA)—R/WC.
1 = The ICH2 has received a byte (for Block Read commands) or if it has completed transmission
7
of a byte (for Block Write commands). This bit will be set even on the last byte of the transfer. It
will not be set when transmission is due to the Alert On LAN* heartbeat.
0 = Cleared by writing a 1 to the bit position.
In Use Status (INUSE_STA)—R/WC (special). This bit is used as semaphore among various
independent software threads that may need to use the ICH2’s SMBus logic and has no other effect
on Hardware.
6 _{0 = After a full PCI reset, a read to this bit returns a 0.}
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
SMBus Alert Status (SMBALERT_STA)—R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#.
5 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by
software writing a 1 to the bit position or by RSMRST# going low.
If the signal is programmed as a GPIO, then this bit will never be set.
Interrupt/SMI# was Failed Bus Transaction (FAILED)—R/WC.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
4
the KILL bit being set to terminate the host transaction.
0 = Cleared by writing a 1 to the bit position.
Bus Error (BUS_ERR)—R/WC.
3 ^{1 = The source of the interrupt of SMI# was a transaction collision.}
0 = Cleared by writing a 1 to the bit position.
Device Error (DEV_ERR)—R/WC.
1 = The source of the interrupt or SMI# was due to one of the following:
• Illegal Command Field,
2
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.]
0 = Software resets this bit by writing a 1 to this location. The ICH2 will then deassert the interrupt
or SMI#.
Interrupt/SMI# was Successful Completion (INTR)—R/WC (special). This bit can only be set by
termination of a command. INTR is not dependent on the INTREN bit of the Host Controller Register
(offset 02h); it is only dependent on the termination of the command. If the INTREN bit is not set, the
INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in
1 _{this non-interrupt case.}
1 = The source of the interrupt or SMI# was the successful completion of its last command.
0 = Software resets this bit by writing 1 to this location. The ICH2 then deasserts the interrupt or
SMI#.
Host Busy (HOST_BUSY)—RO.
1 = Indicates that the ICH2 is running a command from the host interface. No SMB registers should
be accessed while this bit is set, except the Block Data Byte Register. The Block Data Byte
0
register can be accessed when this bit is set only when the SMB_CMD bits in the Host Control
register are programmed for Block command or I²C Read command. This is necessary in order
to check the BYTE_DONE_STS bit.
0 = Cleared by the ICH2 when the current transaction is completed.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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