82801BA Datasheet, PDF (169/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.15.4
Ultra ATA/66 Protocol
In addition to Ultra ATA/33, the ICH2 supports the Ultra ATA/66 protocol. The Ultra ATA/66
protocol is enabled via configuration bits 3:0 at offset 54h. The two protocols are similar, and are
intended to be device driver compatible. The Ultra ATA/66 logic can achieve transfer rates of up to
66 MB/s.
To achieve the higher data rate, the timings are shortened and the quality of the cable is improved
to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and
will still plug into the standard IDE connector. The Ultra ATA/66 protocol also supports a 44 MB/s
mode.
5.15.5
Ultra ATA/100 Protocol
When the ATA_FAST bit is set for any of the 4 IDE devices, the timings for the transfers to and
from the corresponding device run at a higher rate. The ICH2 Ultra ATA/100 logic can achieve
read transfer rates up to 100 MB/s and write transfer rates up to 88.9 MB/s.
The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further
cable improvements are required when implementing Ultra ATA/100.
5.15.6 Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing
Register and the IDE Configuration Register. Different timings can be programmed for each drive
in the system. The Base Clock frequency for each drive is selected in the IDE Configuration
Register. The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base
Clock) are programmed in the Synchronous DMA Timing Register. The Cycle Time represents the
minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the
number of Base Clock periods that the ICH2 will wait from deassertion of DMARDY# to the
assertion of STOP when it desires to stop a burst read transaction.
Note:
The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT)
must be set for 3 Base Clocks. The ICH2, thus, toggles the write strobe signal every 22.5 ns,
transferring two bytes of data on each strobe edge. This means that the ICH2 performs Mode 5
write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the
ATA/100 device; the ICH2 supports reads at the maximum rate of 100 MB/s.
5.15.7 Mobile IDE Swap Bay (82801BAM ICH2-M only)
To support a mobile swap bay, the ICH2-M allows the IDE output signals to be tri-stated and input
buffers to be turned off. This should be done prior to the removal of the drive.
The output signals can also be driven low. This can be used to remove charge built up on the
signals.New configuration bits are included in the IDE I/O Configuration Register, offset 54h in
the IDE PCI configuration space.
WARNING: The software should NOT attempt to control the outputs (either tri-state or driving
low), while an IDE transfer is in progress. Unpredictable results could occur,
including a system lockup.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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