82801BA Datasheet, PDF (375/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
Bit
Description
Configure Flag (CF)—R/W. This bit has no effect on the hardware. It is provided only as a
semaphore service for software.
6
1 = HCD software sets this bit as the last action in its process of configuring the Host Controller.
0 = Indicates that software has not completed host controller configuration.
Software Debug (SWDBG)—R/W. The SWDBG bit must only be manipulated when the controller is
in the stopped state. This can be determined by checking the HCHalted bit in the USBSTS register.
1 = Debug mode. In SW Debug mode, the Host Controller clears the Run/Stop bit after the
5
completion of each USB transaction. The next transaction is executed when software sets the
Run/Stop bit back to 1.
0 = Normal Mode.
Force Global Resume (FGR)—R/W.
1 = Host Controller sends the Global Resume signal on the USB, and sets this bit to 1 when a
resume event (connect, disconnect, or K-state) is detected while in global suspend mode.
4
0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal.
At that time all USB devices should be ready for bus activity. The 1 to 0 transition causes the
port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed.
Enter Global Suspend Mode (EGSM)—R/W.
1 = Host Controller enters the Global Suspend mode. No USB transactions occur during this time.
The Host Controller is able to receive resume signals from USB and interrupt the system.
3
Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit.
0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at
the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0.
Global Reset (GRESET)—R/W.
1 = Global Reset. The Host Controller sends the global reset signal on the USB and then resets all
its logic, including the internal hub registers. The hub registers are reset to their power on state.
2
Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the Host
Controller does not send the Global Reset on USB.
0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified in Chapter 7
of the USB Specification.
Host Controller Reset (HCRESET)—R/W. The effects of HCRESET on Hub registers are slightly
different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the
Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of
the Host Controller including the Connect/Disconnect state machine (one for each port). When the
Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated
to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual
disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1
1 ^{(connect status change) and bit 3 (port enable/disable change) of the PORTSC to get set. The}
disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the
connect and low-speed detect will take place, and bits 0 and 8 of the PORTSC will change
accordingly.
1 = Reset. When this bit is set, the Host Controller module resets its internal timers, counters, state
machines, etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated.
0 = Reset by the Host Controller when the reset process is complete.
Run/Stop (RS)—R/W. When set to 1, the ICH2 proceeds with execution of the schedule. The ICH2
continues execution as long as this bit is set. When this bit is cleared, the ICH2 completes the
current transaction on the USB and then halts. The HC Halted bit in the status register indicates
when the Host Controller has finished the transaction and has entered the stopped state. The Host
0
Controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus
errors.
1 = Run
0 = Stop
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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