82801BA Datasheet, PDF (356/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.1
10.1.2
VID—Vendor ID Register (IDE—D31:F1)
Offset Address:
Default Value:
Lockable:
00–01h
8086h
No
Attribute:
Size:
Power Well:
RO
16-bit
Core
Bit
Description
15:0 Vendor ID Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h
DID—Device ID Register (IDE—D31:F1)
Offset Address:
Lockable:
Default Value:
02–03h
No
244Bh (82801BA ICH2)
244Ah (82801BAM ICH2-M)
Attribute:
Size:
Power Well:
RO
16-bit
Core
10.1.3
Bit
Description
15:0 Device ID Value. This is a 16 bit value assigned to the ICH2 IDE controller.
CMD—Command Register (IDE—D31:F1)
Address Offset: 04h–05h
Default Value: 00h
Attribute:
Size:
RO, R/W
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back to Back Enable (FBE)—RO. Reserved as 0.
SERR# Enable—RO. Reserved as 0.
Wait Cycle Control—RO. Reserved as 0.
Parity Error Response—RO. Reserved as 0.
VGA Palette Snoop—RO. Reserved as 0.
Postable Memory Write Enable (PMWE)—RO. Reserved as 0.
Special Cycle Enable (SCE)—RO. Reserved as 0.
Bus Master Enable (BME)—R/W. Controls the ICH2’s ability to act as a PCI master for IDE Bus
Master transfers.
Memory Space Enable (MSE)—RO. Reserved as 0.
I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy IDE ports (both Primary and Secondary) as well as the Bus
Master IO registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
Note: Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
disable the Primary or Secondary I/O spaces.
10-2
82801BA ICH2 and 82801BAM ICH2-M Datasheet