82801BA Datasheet, PDF (353/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10.6
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +2Ch
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
See bit description
Bit
Description
31:14, 10:9,
5, 2
(ICH2)
31:14, 10:9, 6,
5, 2
(ICH2-M)
Reserved
13:11, 8
GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both active-
low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input
signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. In the S3, S4
or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The
setting of these bits will have no effect if the corresponding GPIO is programmed as an
output. These bits correspond to GPIO that are in the Resume well, and will be reset to their
default values by RSMRST# but not by PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input
pin to be high.
1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input
pin to be low.
7:6, 4:3, 1:0
(ICH2)
7, 4:3, 1:0
(ICH2-M)
GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both active-
low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input
signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. The setting of
these bits will have no effect if the corresponding GPIO is programmed as an output. These
bits correspond to GPIO that are in the Core well, and will be reset to their default values by
PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input
pin to be high.
1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input
pin to be low.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-91