82801BA Datasheet, PDF (346/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.9.10
9.9.11
9.9.12
TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address:
Default Value:
Lockable:
TCOBASE +0Ch (Message 1) Attribute:
TCOBASE +0Dh (Message 2)
00h
Size:
No
Power Well:
R/W
8-bit
Resume
Bit
Description
TCO Message (TCO_MESSAGE[n])—R/W.The value written into this register will be sent out via
7:0 the SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this
register to indicate its boot progress which can be monitored externally.
TCO_WDSTATUS—TCO2 Control Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 0Eh
00h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
Watchdog Status (WDSTATUS)—R/W. The value written to this register will be sent in the Alert On
7:0
LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
TCOBASE + 10h
03h
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved.
IRQ12 Cause (IRQ12_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ12 signal
1 as received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to
receive IRQ12 assertions from a SERIRQ device.
IRQ1 Cause (IRQ1_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ1 signal as
0 received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to
receive IRQ1 assertions from a SERIRQ device.
9-84
82801BA ICH2 and 82801BAM ICH2-M Datasheet