82801BA Datasheet, PDF (85/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.3.1.5 SYNC
Valid values for the SYNC field are listed in Table 5-7.
Table 5-7. SYNC Bit Definition
Bits[3:0]
Indication
0000
0101
0110
1001
1010
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request
deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait states. For bus master cycles, the ICH2 does not use this
encoding. It will instead use the Long Wait encoding (see next encoding below).
Long Wait: Part indicating wait states; many wait states will be added. This encoding driven by
the ICH2 for bus master cycles, rather than the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more
DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers
and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal
on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this
transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request
deassertion and no more transfers desired for that channel.
NOTE: All other combinations are Reserved.
5.3.1.6 SYNC Time-out
There are several error cases that can occur on the LPC interface. Table 5-8 indicates the failing
case and the ICH2 response.
Table 5-8. ICH2 Response to Sync Failures
Possible Sync Failure
ICH2 Response
ICH2 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC
after 4 consecutive clocks. This could occur if the processor tries to access an
I/O location to which no device is mapped.
ICH2 drives a Memory, I/O, or DMA cycle, and a peripheral drives more than 8
consecutive valid SYNC patterns to insert wait states using the Short (‘0101b’)
encoding for SYNC. This could occur if the peripheral is not operating properly.
ICH2 starts a Memory, I/O, or DMA cycle, and a peripheral drives an invalid
SYNC pattern. This could occur if the peripheral is not operating properly or if
there is excessive noise on the LPC interface.
ICH2 aborts the cycle after
the 4^th clock.
Continues waiting
ICH2 aborts the cycle when
the invalid Sync is
recognized.
NOTE: There may be other peripheral failure conditions; however, these are not handled by the ICH2.
5.3.1.7
SYNC Error Indication
The SYNC protocol allows the peripheral to report an error via the LAD[3:0] = 1010b encoding.
The intent of this encoding is to give peripherals a method of communicating errors to aid higher
layers with more robust error recovery.
If the ICH2 was reading data from a peripheral, data will still be transferred in the next two nibbles.
This data may be invalid; however, it must be transferred by the peripheral. If the ICH2 was writing
data to the peripheral, the data had already been transferred.
In the case of multiple byte cycles (e.g., for memory and DMA cycles) an error SYNC terminates
the cycle. Therefore, if the ICH2 is transferring 4 bytes from a device and the device returns the
error SYNC in the first byte, the other three bytes are not transferred.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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