82801BA Datasheet, PDF (366/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.2.2
10.2.3
BMIS[P,S]—Bus Master IDE Status Register
Address Offset:
Default Value:
Primary: 02h
Secondary: 0Ah
00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
7 Reserved. Returns 0.
Drive 1 DMA Capable—R/W.
0 = Not Capable.
6 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this}
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE
to the PCI bus.
Drive 0 DMA Capable—R/W.
0 = Not Capable.
5 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this}
channel is capable of DMA transfers and that the controller has been initialized for optimum
performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE
to the PCI bus.
4:3 Reserved. Returns 0s.
Interrupt—R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt
line (IRQ14 for the Primary channel and IRQ15 for Secondary).
1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is
masked in the 8259 or the internal I/O APIC. When this bit is read as a one, all data transferred
2
from the drive is visible in system memory.
0 = This bit is cleared by software writing a '1' to the bit position. If this bit is cleared while the
interrupt is still active, this bit will remain clear until another assertion edge is detected on the
interrupt line.
Error—R/WC.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
1
data on PCI.
0 = This bit is cleared by software writing a '1' to the bit position.
Bus Master IDE Active (ACT)—RO.
1 = Set by the ICH2 when the Start bit is written to the Command register.
0 = This bit is cleared by the ICH2 when the last transfer for a region is performed, where EOT for
0
that region is set in the region descriptor. It is also cleared by the ICH2 when the Start bit is
cleared in the Command register. When this bit is read as a zero, all data transferred from the
drive during the previous bus master command is visible in system memory, unless the bus
master command was aborted.
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register
Address Offset:
Default Value:
Primary: 04h
Secondary: 0Ch
All bits undefined
Attribute:
Size:
R/W
32 bits
Bit
Description
31:2
Base address of Descriptor table (BADDR)—R/W. Corresponds to A[31:2]. The Descriptor Table
must be DWord aligned. The Descriptor Table must not cross a 64 KB boundary in memory.
1:0 Reserved.
10-12
82801BA ICH2 and 82801BAM ICH2-M Datasheet