DS643 Datasheet, PDF (99/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
MIG Spartan-3 FPGA PHY Template Router and DQ/DQS Data Capture Logic
The proper implementation of the DQ/DQS data capture logic requires specific pinout, timing, and placement
constraints which include PIN, LUT, BEL, SLICE and MAXDELAY elements. This also includes the usage of
template routes during Place and Route. The correct placement and routing of these components should be verified
using FPGA Editor.
See the device-specific Memory Interface Solutions User Guide, under the “DDR2 Debug Guide” >“Debugging the
Spartan-3 FPGA Design”> Verify Placement and Routing.” The steps needed to check the placement and routing of
the Spartan-3 FPGA MIG PHY are described in that section.
MIG Spartan-3 FPGA PHY MAXDELAY Timing Constraints
When running the place and route tools, Spartan-3 FPGA MPMC designs might generate timing errors on the
maxdelay constraints in the MPMC UCF. If this occurs, check the <EDK_project>/implementation/system.twr
file for the errors. If the worst case path is within the range of allowable delays mentioned in the comments of the
MIG UCF, the constraint can be relaxed to allow timing to pass. MAXDELAY constraints should not be relaxed beyond
the range of values described in the UCF comments. It might take several iterations of the tools to resolve the
MAXDELAY timing constraints so the design meets timing. Alternatively, you can proceed with the design and allow
for false timing errors in the MPMC Spartan-3 FPGA PHY logic.
MIG Spartan-3 FPGA PHY Debug Tips and Hints
For Spartan-3 FPGA MIG designs that do not work, the following debugging steps could help in the debug process:
1. Perform the placement and routing checks using FPGA Editor.
2. Check that the MicroBlaze processor can connect to XMD and that simple XMD reads and writes to LMB block
RAM are working. This establishes that the basic processor subsystem is working.
3. Check the PAR report and ensure that all I/O signals are located.
4. If reads from memory space return the same data value across all memory locations, this is a symptom of a hang
in the PHY. This could be caused by any of the following:
- Incorrect connections on the DQS_DIV_I/DQS_DIV_O loopback trace
- Problems with the DQS nets
- Incorrect template router nets (see #1)
- Problems with the generation or conversion of the MIG UCF
5. For data corruption errors or hangs, additional debug might be required by using the ChipScope™ debugging
tool to probe the signals inside the Spartan-3 FPGA PHY block. Signals that can be checked are:
a. PHY read FIFO data out signals. (Two FIFOs per byte lane, one for posedge data and one for negedge data.)
Monitor these signals to check the read data strobed in by the DQS signal.
Read FIFO Data Out = *mpmc_phy_if_0/data_path/data_read/fifo_0_data_out_r<*>
and
*mpmc_phy_if_0/data_path/data_read/fifo_1_data_out_r<*>
b. PHY read FIFO control signals. The signal read_valid_data is used to qualify read data being returned to
the MPMC datapath logic.
The wr_addr and rd_addr_out signals are gray code counters that implement the FIFO Read and Write
pointers driving a dual-port LUT-based RAM for each data bit. A different set of FIFO pointers is
implemented on each byte lane of data for posedge and negedge data.
*mpmc_phy_if_0/data_path/data_read/read_valid_data
*mpmc_phy_if_0/data_path/data_read/fifo_0_wr_addr_out<*><*>
*mpmc_phy_if_0/data_path/data_read/fifo_1_wr_addr_out<*><*>
DS643 February 22, 2013
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Product Specification