DS643 Datasheet, PDF (165/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
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Figure 40: VFBC Write Timing
8
• Bit 31 in command word C1 must be set to 1 for a write operation.
• As shown in Figure 40, the command words C0, C1, C2, and C3 are being written during a data Write. The
command words can be written before, during, or after the data is written.
• Figure 40 also shows one cycle between VFBC<Port_Num>_Wd_End_Burst and the next burst, although zero
to any number of cycles can exist between burst end and the next burst. The number of cycles between bursts
is controlled by the VFBC<Port_Num>_Wd_Write signal. This is the FIFO data push signal asserted by the
VFBC client.
• If the VFBC<Port_Num>_Wd_End_Burst signal is used, it must be asserted during the same cycle as the last
valid data Write and can be on D0-D7 cycles.
• The VFBC<Port_Num>_Wd_End_Burst signal is optional in this diagram and could be set low always. This
signal needs to be used only if the transfer does not end on a 32-word boundary.
• The VFBC can accept a data transfer on every clock cycle where the VFBC Write FIFO is not Full and that the
MPMC memory interface throughput can accommodate the data rate of the VFBC client.
Simultaneous Read and Write Transfers
The VFBC PIM allows Read transfers to occur simultaneously with Write transfers by breaking down each
Read/Write transfer into smaller 128-byte transfers. These 128-byte transfers are interleaved to the external
memory controller switching the transfer type after each transfer (from Read to Write or from Write to Read) if both
types are active.
Data can be popped from the Read FIFO during the same clock cycle that data is pushed onto the Write FIFO.
Single Read or Write commands do not block as long as the data is transferred. Transfer blocking can occur only if
more than one command of the same type (Read or Write) is pushed onto the command FIFO before all the data is
transferred.
For example, when two Write commands followed by a Read command are pushed onto the command FIFO, the
Read transfer is blocked until the first Write transfer has completed.
To avoid transfer blocking, commands should be pushed onto the command FIFO only upon the completion of the
previous command data transfer.
DS643 February 22, 2013
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165
Product Specification