DS643 Datasheet, PDF (45/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Choosing Personality Interface Modules
The provided Personality Interface Modules (PIMs) offer varying connection options and sets of services to the
fabric-side of the MPMC. You can select the PIM in the Base Configuration tab of the MPMC IP Configuration GUI.
The following is a summary of each PIM:
• Xilinx CacheLink PIM (XCL)—Provides a near-direct connection to the MicroBlaze processor cache.
• Soft Direct Memory Access Controller PIM for LocalLink Interfaces (SDMA)—A 32-bit wide Xilinx LocalLink
interface provides medium-throughput performance, but offloads CPU involvement with hardware
scatter-gather handling. Useful for frequent but small data transfers, but requires the most software expertise.
Typically SDMA is used only with an XPS_LL_TEMAC core.
• Processor Local Bus Version 4.6 PIM (PLB)—A general interface used on most EDK IP cores. The PLB is
suggested to be used for the most forward-compatibility.
• PowerPC 440 processor Memory Controller PIM (PPC440MC)—Provides lowest latency connection when
using the PowerPC 440 processor in Virtex-5 FPGAs.
• Video Frame Buffer Controller PIM (VFBC)—A two-dimensional DMA core which also provides
asynchronous clocking from MPMC_Clk0. High-latency, but high-throughput operation for very long bursts,
such as entire video frames.
• Native Port Interface PIM (NPI)—The highest performance general PIM. All other PIMs except for MCB
connect through an NPI interface. The NPI PIM is specific to the MPMC, and future support on Xilinx memory
controllers is unplanned, thus limiting forward-compatibility.
• MCB PIM (MCB)—Spartan-6 FPGA only PIM providing raw access to the memory controller block for highest
performance. Forward-compatibility is unplanned on FPGA families.
Estimates on PIM performance can be found in the MPMC Latency and Throughput, page 193. Total system
throughput can be estimated by a weighted average of each PIMs throughput by the percentage of transactions on
each PIM.
Upgrading MPMC Versions
This section describes how to upgrade the MPMC. In general, the EDK revup tool updates the MPMC inside a
particular major version number automatically without user interaction.
For major version upgrades, manual changes are required. All major version changes require at least the manual
change of the version number. This is best accomplished by editing HW_VER parameter of the MPMC in the system
MHS file.
MPMC should not need any special handling besides increasing the version number. Additional information can
also be found in the MPMC change log.
From MPMCv3 Virtex-5 FPGA DDR2 and Spartan-3 FPGA MIG PHYs
See Standalone Flow: Migrating an MPMCv3 Design to MPMCv5, page 95 when upgrading from MPMC3 to later
MPMC designs when a MIG-based Virtex-5 FPGA DDR2 PHY is used or any Spartan-3/3A/3AN/3E FPGA MIG
PHY is used. In certain cases, the Spartan-3 FPGA pinout might no longer be MIG compatible, requiring the use of
the Static PHY Interface, page 103.
From MPMCv4 Virtex-5 FPGA DDR2 MIG PHYs
See Standalone Flow: Migrating an MPMCv4 Virtex-5 FPGA DDR2 Design to MPMCv5, page 95 when upgrading
from MPMC4 to MPMC5 with a Virtex-5 FPGA DDR2 MIG PHY.
DS643 February 22, 2013
www.xilinx.com
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Product Specification