DS643 Datasheet, PDF (162/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
• Independently configurable write and read data widths of 8, 16, 32, or 64 bits.
• Configurable FIFO depths.
• Configurable almost full and almost empty flags.
• Independent Write, Read, and command FIFO resets.
• Flushable data FIFOs.
VFBC Overview
The VFBC is a connection layer between video clients and the MPMC. Because video systems are inherently
heterogeneous (given the wide variety of video formats and transmission), the VFBC provides key features to
address the typical video system.
The VFBC also includes separate asynchronous FIFO interfaces for command input, Write data input, and Read
data output. This is useful to decouple the video IP from the memory clock domain.
Figure 38 shows the VFBC interfaces. The interfaces are discussed in more detail in the following subsections. See
VFBC PIM I/O Signal, page 27 for more information on the individual signals for each VFBC interface.
Figure 38 shows a block diagram of the VFBC interface.
X-Ref Target - Figure 38
NPI
VFBC
Command
Fetch
Command
FIFO
Interface
Command
Signals
NPI
Signals
NPI
Formatter
Burst Controller
Read Data
FIFO
Interface
Write Data
FIFO
Interface
Read Data
Signals
Write Data
Signals
X10910
Figure 38: VFBC High-Level Block Diagram
DS643 February 22, 2013
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Product Specification