DS643 Datasheet, PDF (75/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Performance Monitoring Usage Example
An example PM session includes the following steps:
1. Disable any currently enabled PMs by writing zeros to the Performance Monitor Control register.
2. Clear the PM counters by writing ones to the Performance Monitor Clear register.
3. Wait for the clear operation to complete by polling the Performance Monitor Status register for all PMs bits set
as one.
4. Clear PM status by writing ones to the Performance Monitor Status register.
5. Enable PM counting by writing ones to the Performance Monitor Control register.
6. Execute user task to be monitored.
7. Stop the PM counting by writing ones to the Performance Monitor Control register.
8. Read each data bin value, typically looping through each set of 32 data bins, read/write set, qualifier set, and
finally each PM.
9. Read the Performance Monitor Global Cycle Count register for total test time.
10. Read the Performance Monitor Dead Cycle Count register of each PM for cycles lost to arbitration grant delays.
11. Prepare for next task monitoring by either re enabling the PMs or executing the clear process.
Performance Monitor Registers
PM registers detailed in the following subsections are available that perform these actions:
• Capture performance statistics (PMCTRL)
• Monitor the status of the clear issued to the PM data bins (PMSTATUS)
• Contain the current value of the global cycle counter (PMGCC)
• Contain the current value of the dead cycle counter for each port (PMx_DCC)
• Contain the transaction information for the performance monitors (PMx_DATA_BINx)
The PM registers are:
• Performance Monitor Control Register
• Performance Monitor Clear Register
• Performance Monitor Status Register
• Performance Monitor Global Cycle Count Register
• Performance Monitor Dead Cycle Count Register
• Performance Monitor Data Bin Registers
DS643 February 22, 2013
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Product Specification