DS643 Datasheet, PDF (71/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
ECC Parity Field Bit Error Count Register
The ECC Parity Field Bit Error Count register (ECCPEC) records the number of bit errors that occurred in the ECC
parity field during the memory transaction. ECC logic corrects detected parity field bit errors. When the value in
this register reaches 4095 (the maximum count), the next parity field bit error detected is not counted. When using
the force error feature, the number of errors detected might not be as expected because the force error feature counts
the number of memory data beats that have errors, not the number of NPI data beats that have errors. Because the
Read_Modify_Write might read more data than NPI requested, the count can be misleading. The ECC logic
corrects the detected single-bit errors. When the value in this register reaches 4095 (the max count), the next
single-bit error detected is not counted.
Table 47 describes the bit values for the ECCPEC.
Table 47: ECCPEC Bit Definitions
Bit(s)
Name
Core Reset
Access Value
Description
0:19
Reserved
20:31
PEC
R/ROW⁽¹⁾
Parity Field Bit Error Count: Indicates the number of errors that occurred
0 in the parity field bits during the last memory transactions. The maximum
error count is 4095.
Notes:
1. ROW = Reset On Write. Any write operation to the ECCPEC register resets the register.
ECC Error Address Register
Table 48 describes the bit values for the ECC Error Address (ECCADDR) register.
Table 48: ECCADDR Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0:31 ECCERRADDR
RO
ECC Error Address: Indicates the physical ECC address
N/A
corresponding to an ECC error reported by the ECC Status register
(ECCS). This register value is only valid when an error is actively
reported in the ECCS.
Device Global Interrupt Enable Register
The Device Global Interrupt Enable register (DGIE) is used to globally enable the final interrupt output from the
ECC interrupt service. Table 49 describes the bit values for the DGIE.
Table 49: DGIE Register Bit Definitions
Bit(s)
Name
Core Access
Reset Value
Description
Global Interrupt Enable:
0
GIE
R/W
0
0 = Interrupts disabled.
1 = Interrupts enabled.
1-31
Reserved
Note: IP Interrupt Status Register
DS643 February 22, 2013
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Product Specification