DS643 Datasheet, PDF (88/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
The example in Figure 9 has the following specified parameters:
C_MEM_TYPE = “DDR2”
C_INCLUDE_ECC_SUPPORT = 1
C_MEM_CLK_WIDTH = 1
C_MEM_ODT_WIDTH = 2
C_MEM_CE_WIDTH = 1
C_MEM_CS_N_WIDTH = 2
C_MEM_ADDR_WIDTH = 13
C_MEM_BANKADDR_WIDTH = 2
C_MEM_DATA_WIDTH = 64
C_MEM_NUM_RANKS = 2
C_MEM_NUM_DIMMS = 1
In this example:
• The DDR2_CS_n[0] signal is connected to one rank of memory and DDR2_CS_n[1] is connected to the other rank
of memory. The DDR2_ODT[0] signal is connected to one rank of memory and DDR2_ODT[1] is connected to the
other rank of memory.
• Within a particular rank, the signals DDR2_CS_n and DDR2_ODT are connected to each memory in the rank.
Some memory manufactures have specific recommendations for how these signals should be connected. For
example, when using a dual rank DIMM, the recommendation might be to assert DDR2_ODT on the same rank
that DDR2_CS_n is asserted (as shown in Figure 9). Other recommendations might be to assert DDR2_ODT on to
opposite rank that the DDR2_CS_n is asserted, which can be achieved by swapping DDR2_ODT[0] and
DDR2_ODT[1].
• All clock, addresses, and other control signals are also connected to each memory.
• The DDR2_DQ, DDR2_DQS, DDR2_DQS_n, and DDR2_DM signals do not go to all discrete memory components.
Instead, 16 bits of DDR2_DQ go to one memory in each rank and 2 bits of DDR2_DQS, DDR2_DQS_n, and DDR2_DM
go to one memory in each rank. The only exception is the ECC memory. When C_MEM_DATA_WIDTH is set to 64,
there are 8 ECC bits. Because the memory has 16 bits; 8 of the DQ bits, the UDQS, the UDQS numbers, and the UDM
are left unconnected. All other pins are connected on the memory.
The parameters C_MEM_CLK_WIDTH, C_MEM_CE_WIDTH, C_MEM_CS_N_WIDTH, and C_MEM_ODT_WIDTH can be used
to replicate the CLK, CKE, CSn, and ODT outputs of the MPMC to match the board schematics. Care must be taken
with C_MEM_CS_N_WIDTH and C_MEM_ODT_WIDTH as these parameters must be an integer multiple of
C_NUM_RANKS*C_NUM_DIMMS.
DS643 February 22, 2013
www.xilinx.com
88
Product Specification