DS643 Datasheet, PDF (168/216 Pages) Xilinx, Inc – Soft Direct Memory Access (SDMA) support

LogiCORE IP Multi-Port Memory Controller (v6.06.a)
Table 87: VGA Video Display Command Packet Data Structure
Command Word 0
Command Word 1
Command Word 2
31:15
Reserved
14:0
X Size
31
30:0
31:24
Write_NotRead Start Address Reserved
23:0
Y Size
0x0000_A00
0x100E_15A0
0x0000_01DF
Command Word 3
31:24
Reserved
23:0
Stride
0x0000_1E00
Several video functions can be performed by changing the Start Address within Command Word 1 during each
video blank interval. For example, to:
• Cycle through multiple frame stores in external memory
• Perform a pan-scan on a VGA display of a rescaled 16:9 source when combined with video scaler
Line Mode 720p
The following example is of a 720p frame being Read from external memory as individual lines. This example
shows one transfer which is repeated for each line in the video. Each 720p video frame includes 720 line transfers.
Each transfer has a different Start Address.
In this example, the VFBC command interface and read interface are reset during the beginning of each line during
the horizontal blank interval. The resets are performed to mitigate system-level error conditions such a cable being
removed, from which user logic protocol violations could cause VFBC hangs or other unexpected behavior. The
resets thus bound the duration of unexpected VFBC behavior and are not required during normal operation. The
VFBC:MPMC_CLK frequency ratio of this example can be inferred from Figure 43 to be 1:1 or less to satisfy the
Cmd/Rd_Reset assertion and deassertion requirements.
Following the reset, the read command is written to the VFBC command interface. The VFBC read interface
becomes non-empty several cycles following the command and data can be popped off of the read interface FIFO.
X-Ref Target - Figure 43
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+B%ODQN
9)%&3RUWB180!B&PGB5HVHW5GB5HVHW
9)%&3RUWB180!B&PGB:ULWH
9)%&3RUWB180!B&PGB'DWD>@
9)%&3RUWB180!B5GB5HDG
9)%&3RUWB180!B5GB'DWD 2XW
9)%& 3RUWB180!B 5GB(QGB%XUVW
9)%&3RUWB180!B5GB(PSW\ 2XW
& & & &
' ' ' ' ' ' ' '
' ' ' ' $N  $N  $N  $N 
;
Figure 43: Lin Mode 720p Transfers
Note: The VFBC<Port_Num>_Rd_End_Burst signal is optional but can be asserted High during the last cycle that the
VFBC<Port_Num>_Rd_Rd_Read is asserted High per line transfer. In this example n=1280.
Table 88 shows the command words written to the command interface during the horizontal blank interval for the
transfer of the first 720 line.
DS643 February 22, 2013
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Product Specification